News
Q▪Kernel is now open source!
With the release of Q▪Kernel v6.0 we have split Q▪Kernel into Q▪Kernel-Free and Q▪Kernel-Pro. Along with this new Lisencing model Q▪Kernel has new inprovements inluding:
- Improved performance for interrupt processing
- Lower power consumption
- Interrupt pre-emptive processing and synchronization processing.
- Full support of the PIC24E and dsPIC33E
- Optimized for MPLAB-X with support for XC16 and C30
- EDS Thread Stacks which significantly extends the capacity of the PIC24E and dsPIC33E
- Ready for the Q-Viewer MPLAB-X plugin (Available Jan 2014)
New release: v5.0
A new version of Q-Kernel is available for existing users. Please contact QuasarSoft to get the latest version which include the following:
- Optimized for MPLAB-X and XC16
- Support for message types
- High-speed CRC and randomize functions
- More in-line code for better performance
- Better support for EDS memory
New release: Version 4.0
Version 4.0 of Q▪Kernel is now available for download. The new version contains added some new excided features:
- Full support of the PIC24E.
- Memory management of Extended Data Space.
- EDS Thread Stacks which significantly extends the capacity of the PIC24E.
- Improved Segmented Interrupt Architecture where every service now has an ISR equivalent.
Some of the devices in the 16-bit PIC line, including the PIC24E, support Extended Data Space memory management and this will make it possible to address many megabytes of RAM. To address this memory the system uses 32-bit pointers. Q▪Kernel support Extended Data Space as variable memory blocks. This feature allows the user to simple specify commands like qEdsAlloc(1000) to allocate 1000 bytes of memory in EDS. Allocation of memory is 100% deterministic and there is no external fragmentation.
Version 4.0 supports EDS Thread Stacks, meaning that the stack space for a thread can be allocated in EDS while the thread still operate at full speed without wait states. This feature allows the developer to create much more threads and extends the capacity of the PIC24 without effort. The 70 MIPS PIC24E now directly competes with smaller 32-bit devices including the PIC32MX. The developer just develops the application as a number of 16-bit threads that work together as one big application.
The Segmented Interrupt Architecture defers some services if the system is in a critical section. Q▪Kernel has an ISR equivalent for every service which handles the internals completely automatic. So qEvtSignalISR() has the same functionality as qEvtSignal() but one can be called from an ISR and the other can be called from a thread.
See the complete feature list on the download page.
Existing customers with a support contract will get this new version free.
New release: Version 3.5
Version 3.5 of Q▪Kernel builds on the strength of the previous version by improving the performance of the system and including valuable features like publish/subscribe.
Some of the other new features are:
- Faster scheduling engine that schedules tick-less with a scheduling granularity of one micro-second.
- Message handling has been approved and messages can now be sent and received by queues and pipes and message can be published.
- The publish/subscribe mechanism provides decoupling between device drivers and the application. This improves code re-use, less testing, less development time and improves agility. Please read chapter 19 of the user guide for more detailed information.
- Fixed memory pools are improved and allocation is more determenistic.
- The source of Q▪Kernel is available for qualified customers with any Full Licenses.
See the complete feature list on the download page.
Existing customers with a support contract will get this new version free.
New release: Version 3.0
Version 3.0 of Q▪Kernel has been released. Some notable new features include low power management, tick-less operation, and fiber and thread tracking. Please visit our Products page to learn more about the added functionality of this version.
RTOS class held at Microchip MASTERs
Our project manager, John Groenland, will be giving a lecture on August 27 and 28. The class explains in detail the fundamental differences between the two main architectures, the "segmented interrupt architecture" and the "unified interrupt architecture". Without focusing on any particular RTOS, this class will provide attendees with information allowing them to make informed decisions when selecting an RTOS architecture. Basic RTOS terminology, such as "dual mode", "zero interrupt latency", "top and bottom halves" and "interrupt jitter" will be covered. The class then goes on to explain different power saving mechanisms available in RTOSs and provides information on how they affect timing and power consumption.
Joins us at Microchip MASTERs 2010 in Phoenix August 23 – August 28
The Masters 2010 is the premier technical training event for embedded control engineers around the globe. Now in it’s 13 year, the MASTERs conference continues to arm designers of every level with expensive product information and hands on training. Come learn about Q▪Kernel from the same developers who designed the product and walk out with all the information. For more information go to this site: http://techtrain.microchip.com/masters/
New release: Version 2.4
Version 2.4 of Q▪Kernel is faster and we have added some very valuable features like micro-second timing. The scheduling speed has been approved and the whole system functions more than 10% faster.
Some of the new features are:
- Microsecond timer has been extended to allow guaranteed scheduling times. The developer can now specify minimum guaranteed sleep-times independent of the tick clock.
- The low-power functionality was been improved and the developer has full control over the power functions.
- The source of Q▪Kernel is available for qualified customers with any Full Licenses.
See performance information here.
See the complete feature list on the download page.
Existing customers with a support contract will get this new version free.
New in version v2.3
Version 2.3 of Q▪Kernel is faster and contains more functionality than version 2.2. The scheduling speed has been approved and semaphores are now more than 20% faster. This version also supports the PIC30F processor.
Existing customers with a support contract will get this new version free including the new processor support.
See the complete feature list on the download page.
Q▪Kernel for PIC32 is available now!
Q▪Kernel for PIC32 is now available for download. This version combines the quality and versatility of Q▪Kernel V2.2 with the powerful MIPS M4K core and performs excellent. All functionality of Q▪Kernel V2.2 is available and it enables the developer to produce code faster.
See the complete feature list on the download page.
New Release v2.2
Version 2.1 has been extended with a number of features:
- Real Time Clock. This clock is independent of the RTOS clock and provides high accuracy on the long term. The developer can set an unlimited number of real-time clock events and the real time clock provides date and time functions.
- Microsecond timer. This timer allows the developer to measure times with a granularity of 1 microsecond and provides a range for more than 500,000 years without influencing the performance. The timer also provides simple integration with the Tick function in the TCP/IP stack.
- The queued fiber services now accept two arguments. This provides the user with more flexibility to split a critical interrupt in a top and a bottom part
Q▪Kernel is faster than all of its competitors in most categories.
See performance information here.
New in version v2.1
Version 2.1 has been extended to support lightweight threads. The main purpose of lightweight threads is very efficient cooperative multi-threading and minimize memory requirements. Lightweight threads are executed if all threads are in a wait state and there are no interrupts or fibers running. They look a lot like fibers but they run at a low priority in the idle thread.
Lightweight threads are an ideal candidate for low priority, non-time critical drivers. Every application has a number of those, like displaying text on an LCD, logging information in flash, etc. Competitive products use threads for all drivers but applications that use Q▪Kernel can significantly limit resources by using lightweight threads.
As mentioned above lightweight threads look a lot like fibers meaning that all function must be called without blocking. Lightweight treads have a very simple facility to wait a specific time before called again. This unique feature makes lightweight thread simple to use. The download contains an example of a character LCD display driver that explains the techniques discussed.
During creation of a lightweight thread the system creates a context that is presented to the function as pointer to the structure. The first element in the structure must be an unsigned integer that will be decremented every millisecond if not zero. The lightweight thread will only be active if the value of this field is zero. This is a very efficient mechanism to let the lightweight tread wait. The second element in the structure will be filled by the system with the “parameter” specified in qLwtCreate(). The rest of the structure will be filled with zero.
Joins us at Microchip MASTERs 2009 in Phoenix July 27th – August 1st
The Masters 2009 is the premier technical training event for embedded control engineers around the globe. Now in it’s 13 year, the MASTERs conference continues to arm designers of every level with expensive product information and hands on training. Come learn about Q▪Kernel from the same developers who designed the product and walk out with all the information. For more information go to this site: http://techtrain.microchip.com/masters/
Purchase Q▪Kernel-Pro Licenses and/or Pro support.
Download the latest release of the Q▪Kernel source code and documentation.
Get the answers to some common questions about Q▪Kernel
For Q▪Kernel-Pro support contact us.