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Q▪Kernel for PIC24 and dsPIC
The Q▪Kernel version for PIC24 and dsPIC is a full implementation of Q▪Kernel for PIC24F, PIC24H, dsPIC30F and dsPIC33F.
The processors are based on a modified Harvard architecture and implement a 16-bit data bus and a 24-bit instruction bus and use the same base instruction set. The compiler supports a near and far code and data space memory model. Q▪Kernel uses internally a near code model for optimal performance but all external addresses are based on the far code model for optimal application flexibility. All static Q▪Kernel data is near data for optimal performance.
The DSP engine in the dsPIC30F and dsPIC33F can only be used in fibers. We advise to use the DSP in fibers only for optimal use of the dual mode facilities.
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